View LT1999-10_4482677.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

LT1999-10/lt1999-20/ lt1999-50 1 1999fb typical a pplica t ion fea t ures descrip t ion high voltage, bidirectional current sense amplifier the lt ? 1999 is a high speed precision current sense amplifer, designed to monitor bidirectional currents over a wide common mode range. the lt1999 is offered in three gain options: 10v/v, 20v/v, and 50v/v. the lt1999 senses current via an external resistive shunt and generates an output voltage, indicating both magnitude and direction of the sensed current. the output voltage is referenced halfway between the supply voltage and ground, or an external voltage can be used to set the reference level. with a 2mhz bandwidth and a common mode input range of C5v to 80v, the lt1999 is suitable for monitoring currents in h-bridge motor controls, switching power supplies, solenoid currents, and battery charge currents from full charge to depletion. the lt1999 operates from an independent 5v supply and draws 1.55ma. a shutdown mode is provided for minimiz - ing power consumption. the lt1999 is available in an 8-lead msop or sop package. l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. a pplica t ions n buffered output with 3 gain options: 10v/v , 20v/v, 50v/v n gain accuracy: 0.5% max n input common mode voltage range: C5v to 80v n ac cmrr > 80db at 100khz n input offset voltage: 1.5mv max n C3db bandwidth: 2mhz n smooth, continuous operation over entire common mode range n 4kv hbm tolerant and 1kv cdm tolerant n low power shutdown <10a n C55c to 150c operating temperature range n 8-lead msop and 8-lead so (narrow) packages n high side or low side current sensing n h-bridge motor control n solenoid current sense n high voltage data acquisition n pwm control loops n fuse/mosfet monitoring full bridge armature current monitor time (10s/div) 2.5v v out (2v/div) v +in (20v/div) 1999 ta01b v out v +in lt1999 4k 0.8k 160k 160k 2a 0.8k 4k shdn 5v v + v + v + 5v r s 1999 ta01a + ? + ? v s 8 1 2 3 4 7 6 5 0.1f 0.1f v out r g v +in v ?in v ref v shdn v + v +
LT1999-10/lt1999-20/ lt1999-50 2 1999fb a bsolu t e maxi m u m r a t ings differential input voltage +in to Cin (notes 1, 3) ................................. 60v, 10ms +in to gnd, Cin to gnd (note 2) ............. C 5.25v to 88v total supply voltage (v + to gnd) ................................ 6v i nput voltage pins 6 and 8 ................... v + + 0.3v, C0.3v output short-circuit duration (note 4) ............ ind efinite operating ambient temperature (note 5) lt1999c .............................................. C 40c to 85c lt1999i ................................................ C 40c to 85c lt1999h ............................................ C 40c to 125c lt1999mp ......................................... C 55c to 150c (note 1) 1 2 3 4 v + +in ?in v + 8 7 6 5 shdn out ref gnd top view ms8 package 8-lead plastic msop t jmax = 150c, ja = 300c/w 1 2 3 4 8 7 6 5 top view shdn out ref gnd v + +in ?in v + s8 package 8-lead plastic so t jmax = 150c, ja = 190c/w p in c on f igura t ion o r d er i n f or m a t ion lead free finish tape and reel part marking* package description specified temperature range lt1999cms8-10#pbf lt1999cms8-10#trpbf ltfpb 8-lead plastic msop 0c to 70c lt1999ims8-10#pbf lt1999ims8-10#trpbf ltfpb 8-lead plastic msop C40c to 85c lt1999hms8-10#pbf lt1999hms8-10#trpbf ltfpb 8-lead plastic msop C40c to 125c lt1999mpms8-10#pbf lt1999mpms8-10#trpbf ltfqp 8-lead plastic msop C55c to 150c lt1999cs8-10#pbf lt1999cs8-10#trpbf 199910 8-lead plastic so 0c to 70c lt1999is8-10#pbf lt1999is8-10#trpbf 199910 8-lead plastic so C40c to 85c lt1999hs8-10#pbf lt1999hs8-10#trpbf 199910 8-lead plastic so C40c to 125c lt1999mps8-10#pbf lt1999mps8-10#trpbf 99mp10 8-lead plastic so C55c to 150c lt1999cms8-20#pbf lt1999cms8-20#trpbf ltfnz 8-lead plastic msop 0c to 70c lt1999ims8-20#pbf lt1999ims8-20#trpbf ltfnz 8-lead plastic msop C40c to 85c lt1999hms8-20#pbf lt1999hms8-20#trpbf ltfnz 8-lead plastic msop C40c to 125c lt1999mpms8-20#pbf lt1999mpms8-20#trpbf ltfqq 8-lead plastic msop C55c to 150c specified temperature range (note 6) lt1999c .................................................. 0 c to 70c lt1999i ................................................ C 40c to 85c lt1999h ............................................ C 40c to 125c lt1999mp ......................................... C 55c to 150c junction temperature ........................................... 15 0c storage temperature range .................. C 65c to 150c
LT1999-10/lt1999-20/ lt1999-50 3 1999fb e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, 0c < t a < 70c for c-grade parts, C40c < t a < 85c for i-grade parts, and C40c < t a < 125c for h-grade parts, otherwise specifications are at t a = 25c. v + = 5v, gnd = 0v, v cm = 12v, v ref = floating, v shdn = floating, unless otherwise specified. see figure 2. lead free finish tape and reel part marking* package description specified temperature range lt1999cs8-20#pbf lt1999cs8-20#trpbf 199920 8-lead plastic so 0c to 70c lt1999is8-20#pbf lt1999is8-20#trpbf 199920 8-lead plastic so C40c to 85c lt1999hs8-20#pbf lt1999hs8-20#trpbf 199920 8-lead plastic so C40c to 125c lt1999mps8-20#pbf lt1999mps8-20#trpbf 99mp20 8-lead plastic so C55c to 150c lt1999cms8-50#pbf lt1999cms8-50#trpbf ltfpc 8-lead plastic msop 0c to 70c lt1999ims8-50#pbf lt1999ims8-50#trpbf ltfpc 8-lead plastic msop C40c to 85c lt1999hms8-50#pbf lt1999hms8-50#trpbf ltfpc 8-lead plastic msop C40c to 125c lt1999mpms8-50#pbf lt1999mpms8-50#trpbf ltfqr 8-lead plastic msop C55c to 150c lt1999cs8-50#pbf lt1999cs8-50#trpbf 199950 8-lead plastic so 0c to 70c lt1999is8-50#pbf lt1999is8-50#trpbf 199950 8-lead plastic so C40c to 85c lt1999hs8-50#pbf lt1999hs8-50#trpbf 199950 8-lead plastic so C40c to 125c lt1999mps8-50#pbf lt1999mps8-50#trpbf 99mp50 8-lead plastic so C55c to 150c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ o r d er i n f or m a t ion symbol parameter conditions min typ max units v sense full-scale input sense voltage (note 7) v sense = v +in C v Cin LT1999-10 lt1999-20 lt1999-50 l l l C0.35 C0.2 C0.08 0.35 0.2 0.08 v v v v cm cm input voltage range l C5 80 v r in(diff) differential input impedance v indiff = 2v/gain l 6.4 8 9.6 k r incm cm input impedance v cm = 5.5v to 80v v cm = C5v to 4.5v l l 5 3.6 20 4.8 6 m k v osi input referred voltage offset l C750 C1500 500 750 1500 v v v osi /t input referred voltage offset drift 5 v/c a v gain LT1999-10 lt1999-20 lt1999-50 l l l 9.95 19.9 48.75 10 20 50 10.05 20.1 50.25 v/v v/v v/v a v error gain error v out = 2v l C0.5 0.2 0.5 % i b input bias current i(+in) = i(Cin) (note 8) v cm > 5.5v v cm = C5v v shdn = 0.5v, 0v < v cm < 80v l l l 100 C2.35 137.5 C1.95 0.001 175 C1.5 2.5 a ma a i os input offset current i os = i(+in) C i(Cin) (note 8) v cm > 5.5v v cm = C5v v shdn = 0.5v, 0v < v cm < 80v l l l C1 C10 C2.5 1 10 2.5 a a a psrr supply rejection ratio v + = 4.5v to 5.5v l 68 77 db
LT1999-10/lt1999-20/ lt1999-50 4 1999fb e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, 0c < t a < 70c for c-grade parts, C40c < t a < 85c for i-grade parts, and C40c < t a < 125c for h-grade parts, otherwise specifications are at t a = 25c. v + = 5v, gnd = 0v, v cm = 12v, v ref = floating, v shdn = floating, unless otherwise specified. see figure 2. symbol parameter conditions min typ max units cmrr sense input common mode rejection v cm = C5v to 80v v cm = C5v to 5.5v v cm = 12v, 7v p-p , f = 100khz, v cm = 0v, 7v p-p , f = 100khz l l l l 96 96 75 80 105 120 90 100 db db db db e n differential input referred noise voltage density f = 10khz f = 0.1hz to 10hz 97 8 nv/ hz v p-p ref rr ref pin rejection, v + = 5.5v v ref = 3.0v v ref = 3.25v v ref = 3.25v LT1999-10 lt1999-20 lt1999-50 l l l 62 62 62 70 70 70 db db db r ref ref pin input impedance v shdn = 0.5v l l 60 0.15 80 0.4 100 0.65 k m v ref open circuit voltage v shdn = 0.5v l l 2.45 1 2.5 2.5 2.55 2.75 v v v refr ref pin input range (note 9) LT1999-10 lt1999-20 lt1999-50 l l l 1.25 1.125 1.125 v + C 1.25 v + C 1.125 v + C 1.125 v v v i shdn pin pull-up current v + = 5.5v, v shdn = 0v l C6 C2 a v ih shdn pin input high l v + C 0.5 v v il shdn pin input low l 0.5 v f 3db small signal bandwidth LT1999-10 lt1999-20 lt1999-50 2 2 1.2 mhz mhz mhz sr slew rate 3 v/s t s settling time due to input step, v out = 2v 0.5% settling 2.5 s t r common mode step recovery time v cm = 50v, 20ns (note 10) LT1999-10 lt1999-20 lt1999-50 0.8 1 1.3 s s s v s supply voltage (note 11) l 4.5 5 5.5 v i s supply current v cm > 5.5v v cm = C5v v + = 5.5v, v shdn = 0.5v, v cm > 0v l l l 1.55 5.8 3 1.9 7.1 10 ma ma a r o output impedance i o = 2ma 0.15 i src sourcing output current r load = 50 to gnd l 6 31 40 ma i snk sinking output current r load = 50 to v + l 15 26 40 ma v out swing output high (with respect to v + ) r load = 1k to mid-supply r load = open l l 125 5 250 125 mv mv swing output low (with respect to v C ) r load = 1k to mid-supply r load = open l l 250 150 400 225 mv mv t on turn-on time v shdn = 0v to 5v 1 s t off turn-off time v shdn = 5v to 0v 1 s
LT1999-10/lt1999-20/ lt1999-50 5 1999fb e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, C55c < t a < 150c for mp-grade parts, otherwise specifications are at t a = 25c. v + = 5v, gnd = 0v, v cm = 12v, v ref = floating, v shdn = floating, unless otherwise specified. see figure 2. symbol parameter conditions min typ max units v sense full-scale input sense voltage (note 7) v sense = v +in C v Cin LT1999-10 lt1999-20 lt1999-50 l l l C0.35 C0.2 C0.08 0.35 0.2 0.08 v v v v cm cm input voltage range l C5 80 v r in(diff) differential input impedance v indiff = 2v/gain l 6.4 8 9.6 k r incm cm input impedance v cm = 5.5v to 80v v cm = C5v to 4.5v l l 5 3.6 20 4.8 6 m k v osi input referred voltage offset l C750 C2000 500 750 2000 v v v osi /t input referred voltage offset drift 8 v/c a v gain LT1999-10 lt1999-20 lt1999-50 l l l 9.95 19.9 48.75 10 20 50 10.05 20.1 50.25 v/v v/v v/v a v error gain error v out = 2v l C0.5 0.2 0.5 % i b input bias current i(+in) = i(Cin) (note 8) v cm > 5.5v v cm = C5v v shdn = 0.5v, 0v < v cm < 80v l l l 100 C2.35 137.5 C1.95 0.001 180 C1.5 10 a ma a i os input offset current i os = i(+in) C i(Cin) (note 8) v cm > 5.5v v cm = C5v v shdn = 0.5v, 0v < v cm < 80v l l l C1 C10 C10 1 10 10 a a a psrr supply rejection ratio v + = 4.5v to 5.5v l 68 77 db cmrr sense input common mode rejection v cm = C5v to 80v v cm = C5v to 5.5v v cm = 12v, 7v p-p , f = 100khz, v cm = 0v, 7v p-p , f = 100khz l l l l 96 96 75 80 105 120 90 100 db db db db e n differential input referred noise voltage density f= 10khz f = 0.1hz to 10hz 97 8 nv/ hz v p-p ref rr ref pin rejection, v + = 5.5v v ref = 2.75v v ref = 3.25v v ref = 3.25v LT1999-10 lt1999-20 lt1999-50 l l l 62 62 62 70 70 70 db db db r ref ref pin input impedance v shdn = 0.5v l l 60 0.15 80 0.4 100 0.65 k m v ref open circuit voltage v shdn = 0.5v l l 2.45 0.25 2.5 2.5 2.55 2.75 v v v refr ref pin input range (note 9) LT1999-10 lt1999-20 lt1999-50 l l l 1.5 1.125 1.125 v + C 1.25 v + C 1.125 v + C 1.125 v v v i shdn pin pull-up current v + = 5.5v, v shdn = 0v l C6 C2 a v ih shdn pin input high l v + C 0.5 v v il shdn pin input low l 0.5 v f 3db small signal bandwidth LT1999-10 lt1999-20 lt1999-50 2 2 1.2 mhz mhz mhz sr slew rate 3 v/s t s settling time due to input step, v out = 2v 0.5% settling 2.5 s
LT1999-10/lt1999-20/ lt1999-50 6 1999fb e lec t rical c harac t eris t ics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: pin 2 (+in) and pin 3 (Cin) are protected by esd voltage clamps which have asymmetric bidirectional breakdown characteristics with respect to the gnd pin (pin 5). these pins can safely support common mode voltages which vary from C5.25v to 88v without triggering an esd clamp. note 3: exposure to differential sense voltages exceeding the normal operating range for extended periods of time may degrade part performance. a heat sink may be required to keep the junction temperature below the absolute maximum rating when the inputs are stressed differentially. the amount of power dissipated in the lt1999 due to input overdrive can be approximated by: p diss = v + in ? v ? in ( ) 2 8k ? note 4: a heat sink may be required to keep the junction temperature below the absolute maximum rating. note 5: the lt1999c/lt1999i are guaranteed functional over the operating temperature range C40c to 85c. the lt1999h is guaranteed functional over the operating temperature range C40c to 125c. the lt1999mp is guaranteed functional over the operating temperature range C55c to 150c. junction temperatures greater than 125c will promote accelerated aging. the lt1999 has a demonstrated typical life beyond 1000 hours at 150c. note 6: the lt1999c is guaranteed to meet specified performance from 0c to 70c. the lt1999c is designed, characterized, and expected to meet specified performance from C40c to 85c but is not tested or qa sampled at these temperatures. the lt1999i is guaranteed to meet specified performance from C40c to 85c. the lt1999h is guaranteed to meet specified performance from C40c to 125c. the lt1999mp is guaranteed to meet specified performance from C55c to 150c. note 7: full-scale sense (v sense ) gives indication of the maximum differential input that can be applied with better than 0.5% gain accuracy. gain accuracy is degraded when the output saturates against either power supply rail. v sense is verified with v + = 5.5v, v cm = 12v, with the ref pin set to its voltage range limits. the maximum v sense is verified with the ref pin set to its minimum specified limit, verifying the gain error is less than 0.5% at the output. the minimum v sense is verified with the ref pin set to its maximum specified limit, verifying the gain error at the output is less than 0.5%. see note 9 for more information. note 8: i b is defined as the average of the input bias currents to the +in and Cin pins (pins 2 and 3). a positive current indicates current flowing into the pin. i os is defined as the difference of the input bias currents. i os = i(+in) C i(Cin) note 9: the ref pin voltage range is the minimum and maximum limits that ensures the input referred voltage offset does not exceed 3mv over the i, c, and h temperature ranges, and 3.5mv over the mp temperature range. note 10: common mode recovery time is defined as the time it takes the output of the lt1999 to recover from a 50v, 20ns input common mode voltage transition, and settle to within the dc amplifier specifications. note 11: operating the lt1999 with v + < 4.5v is possible, although the lt1999 is not tested or specified in this condition. see the applications information section. symbol parameter conditions min typ max units t r common mode step recovery time v cm = 50v, 20ns (note 10) LT1999-10 lt1999-20 lt1999-50 0.8 1 1.3 s s s v s supply voltage (note 11) l 4.5 5 5.5 v i s supply current v cm > 5.5v v cm = C5v v + = 5.5v, v shdn = 0.5v, v cm > 0v l l l 1.55 5.8 3 1.9 7.1 25 ma ma a r o output impedance i o = 2ma 0.15 i src sourcing output current r load = 50 to gnd l 3 31 40 ma i snk sinking output current r load = 50 to v + l 10 26 40 ma v out swing output high (with respect to v + ) r load = 1k to mid-supply r load = open l l 125 5 250 125 mv mv swing output low (with respect to v C ) r load = 1k to mid-supply r load = open l l 250 150 400 225 mv mv t on turn-on time v shdn = 0v to 5v 1 s t off turn-off time v shdn = 5v to 0v 1 s the l denotes the specifications which apply over the full operating temperature range, C55c < t a < 150c for mp-grade parts, otherwise specifications are at t a = 25c. v + = 5v, gnd = 0v, v cm = 12v, v ref = floating, v shdn = floating, unless otherwise specified. see figure 2.
LT1999-10/lt1999-20/ lt1999-50 7 1999fb typical p er f or m ance c harac t eris t ics input bias current vs input common mode input bias current vs temperature input impedance vs input common mode voltage v cm (v) ?5 i b (ma) 0.5 0 ?1.0 ?1.5 ?0.5 ?2.0 45 25 65 1999 g07 75 80 35 155 55 v + = 5v temperature (c) ?55 i b (a) 146 144 140 134 136 138 142 132 70 20 120 1999 g08 145 45 ?5?30 95 v cm = 80v v cm = 5.5v v shdn = open v indiff = 0v v + = 5v v cm (v) ?5 impedance (k) 100000 10000 100 10 1000 1 45 25 65 1999 g09 75 35 155 55 common mode input impedance differential input impedance supply current vs shdn pin voltage shutdown supply current vs temperature shutdown input bias current vs input common mode supply current vs input common mode supply current vs temperature supply current vs supply voltage v cm (v) ?5 i s (ma) 7 6 4 2 5 3 1 0 45 25 65 1999 g01 75 80 35 155 55 v + = 5v temperature (c) ?55 i s (ma) 1.8 1.7 1.5 1.6 1.4 70 20 120 1999 g02 145 45 ?5?30 95 v + = 5.5v v + = 4.5v v shdn = open v indiff = 0v v cm = 12v supply voltage (v) 0 i s (ma) 4.0 3.0 1.0 2.0 3.5 1.5 2.5 0 0.5 2 4 1999 g03 5 1 3 v cm = 12v 150c 130c 90c 25c ?45c ?55c v shdn (v) 0 i s (ma) 10 0.1 1 0.001 0.01 2 4 1999 g04 5 1 3 t a = 25c t a = 150c t a = ?55c v + = 5v v cm = 12v temperature (c) ?55 i s (a) 10 8 4 2 6 0 70 20 120 1999 g05 145 45 ?5?30 95 v + = 5.5v v + = 4.5v v shdn = 0v v indiff = 0v v cm = 12v v cm (v) 0 i b (na) 1000 10 100 1 40 80 1999 g06 100 20 60 v + = 5v v shdn = 0v v sense = 0v t a = 70c t a = 90c t a = 150c t a =110c t a =130c
LT1999-10/lt1999-20/ lt1999-50 8 1999fb typical p er f or m ance c harac t eris t ics LT1999-10 small signal frequency response gain error vs temperature gain error vs input common mode voltage input referred voltage offset vs temperature and gain option input referred voltage offset vs input common mode voltage temperature (c) ?55 v osi (v) 1500 1000 ?500 ?1000 500 0 ?1500 70 20 120 1999 g10 145 45 ?5?30 95 LT1999-10 lt1999-20 lt1999-50 v cm = 12v 12 units plotted v cm (v) ?5 v osi (v) 1500 1000 ?500 ?1000 500 0 ?1500 45 25 65 1999 g11 75 35 155 55 v + = 5v t a = 25c 12 units plotted LT1999-10 lt1999-20 lt1999-50 temperature (c) ?55 gain error (%) 0.50 0.25 ?0.25 0 ?0.50 70 20 120 1999 g15 145 45 ?5?30 95 v cm = 12v 12 units plotted LT1999-10 lt1999-20 lt1999-50 v cm (v) ?5 gain error (%) 0.50 0.25 ?0.25 0 ?0.50 45 25 65 1999 g16 75 35 155 55 v + = 5v t a = 25c 12 units plotted LT1999-10 lt1999-20 lt1999-50 frequency (khz) 1 gain (db) phase (deg) 30 15 0 ?5 10 25 20 5 ?10 180 45 ?90 ?135 0 135 90 ?45 ?180 10 1000 1999 g12 10000 100 v out = 0.5v p-p at 1khz gain phase lt1999-50 small signal frequency response lt1999-20 small signal frequency response frequency (khz) 1 gain (db) phase (deg) 35 20 5 0 15 30 25 10 ?5 180 45 ?90 ?135 0 135 90 ?45 gain ?180 10 1000 1999 g13 10000 100 v out = 0.5v p-p at 1khz phase frequency (khz) 1 gain (db) phase (deg) 40 25 10 5 20 35 30 15 0 180 45 ?90 ?135 0 135 90 ?45 gain phase ?180 10 1000 1999 g14 10000 100 v out = 0.5v p-p at 1khz
LT1999-10/lt1999-20/ lt1999-50 9 1999fb typical p er f or m ance c harac t eris t ics cmrr vs frequency cmrr vs frequency frequency (khz) 1 cmrr (db) 120 100 80 20 40 60 0 1000 1999 g23 10000 100 10 v cm = 12v v + = 5v t a = 25c 6 units plotted LT1999-10 lt1999-20 lt1999-50 lt1999-50 2v step response settling time LT1999-10 2v step response settling time lt1999-20 2v step response settling time lt1999-50 pulse response time (2s/div) v sense (0.1v/div) v out (1v/div) 1999 g19 v out v sense v out time (1s/div) v out (v) output error (v) 4.5 3.5 1.5 2.5 0.5 4.0 2.0 3.0 1.0 0.100 0.050 ?0.050 0 ?0.100 0.075 ?0.025 0.025 ?0.075 1999 g20 output error v out v out (v) output error (v) 4.5 3.5 1.5 2.5 0.5 4.0 2.0 3.0 1.0 0.20 0.10 ?0.01 0 ?0.20 0.15 ?0.05 0.05 ?0.15 output error time (1s/div) ?1 42 6 1999 g21 7 310 5 9 108 v out (v) output error (v) 4.5 3.5 1.5 2.5 0.5 4.0 2.0 3.0 1.0 0.500 0.250 ?0.250 0 ?0.500 0.375 ?0.125 0.125 ?0.375 time (1s/div) 1999 g22 v out output error LT1999-10 pulse response lt1999-20 pulse response time (2s/div) v sense (0.5v/div) v out (1v/div) 1999 g17 v out v sense time (2s/div) v sense (0.2v/div) v out (1v/div) 1999 g18 v out v sense frequency (khz) 1 cmrr (db) 120 100 80 20 40 60 0 1000 100 1999 g24 10000 10 v cm = 0v v + = 5v t a = 25c 6 units plotted LT1999-10 lt1999-20 lt1999-50
LT1999-10/lt1999-20/ lt1999-50 10 1999fb LT1999-10 common mode rising edge step response v out (0.5v/div) v cm (25v/div) time (0.5s/div) 1999 g25 v cm , t rise 20ns v out LT1999-10 common mode falling edge step response v out (0.5v/div) v cm (25v/div) time (0.5s/div) 1999 g26 v cm , t fall 20ns v out v out (0.5v/div) v cm (25v/div) time (0.5s/div) 1999 g27 v cm , t rise 20ns v out lt1999-20 common mode rising edge step response lt1999-20 common mode falling edge step response v out (0.5v/div) v cm (25v/div) time (0.5s/div) 1999 g28 v cm , t fall 20ns v out typical p er f or m ance c harac t eris t ics lt1999-50 common mode rising edge step response lt1999-50 common mode falling edge step response v out (0.5v/div) v cm (25v/div) time (0.5s/div) 1999 g29 lt1999-50 common mode rising edge step response time (0.5 s / div) v out (0.5 v / div) v cm (25v / div) v cm t rise 20ns v cm , t rise 20ns v out v out (0.5v/div) v cm (25v/div) time (0.5s/div) 1999 g30 v cm , t fall 20ns v out
LT1999-10/lt1999-20/ lt1999-50 11 1999fb typical p er f or m ance c harac t eris t ics lt1999 input referred noise density vs frequency frequency (khz) 0.001 0.01 0.1 noise density (nv/ hz) 1000 100 10 1000 1999 g31 10000 101 temperature (c) ?55 i sc (ma) 40 20 30 10 ?20 0 ?40 ?10 ?30 70 20 120 1999 g32 145 45 ?5?30 95 sinking sourcing temperature (c) ?55 ref pin voltage (v) 3.0 2.5 1.0 2.0 0 1.5 0.5 70 20 120 1999 g33 145 45 ?5?30 95 shdn mode active mode v + = 5v short-circuit current vs temperature ref open circuit voltage vs temperature shdn pin current vs shdn pin voltage and temperature turn-on/turn-off time vs shdn voltage v out vs v sense i s (1ma/div) shdn pin voltage (5v/div) time (1s/div) 1999 g35 v shdn i s shutdown v cm = 12v v sense (v) ?0.25 v out (v) 6 4 5 1 2 3 ?1 ?0.05 0.15 1999 g36 0.25 ?0.15 0.05 v ref = 2.5v LT1999-10 lt1999-20 lt1999-50 0 v shdn (v) 0 i shdn (a) ?2 ?4 ?1 0 ?3 2 4 5 1999 g34 1 3 t a = 150c t a = 25c t a = ?55c v + = 5v v cm = 12v v out vs v sense over the sense absmax range v sense (v) ?60 v out (v) 6 4 5 1 2 3 ?1 ?30 30 1999 g37 60 0 0 v out phase reversal for v sense < ?25v v ref = 2.5v LT1999-10 lt1999-20 lt1999-50
LT1999-10/lt1999-20/ lt1999-50 12 1999fb p in func t ions v + (pins 1, 4): power supply voltage. pins 1 and 4 are tied internally together. the specifed range of operation is 4.5v to 5.5v, but lower supply voltages (down to ap - proximately 4v) is possible although the lt1999 is not tested or characterized below 4.5v. see the applications information section. +in (pin 2): positive sense input pin. Cin (pin 3): negative sense input pin. gnd (pin 5): ground pin. ref (pin 6): reference pin input. the ref pin sets the output common mode level and is set halfway between v + and gnd using a divider made of two 160k resistors. the default open circuit potential of the ref pin is mid-supply. it can be overdriven by an external voltage source cable of driving 80k to a mid-supply potential (see the electrical characteristics table for its specifed input voltage range). out (pin 7): voltage output. v out = a v ? (v sense v osi ), where a v is the gain, and v osi is the input referred off- set voltage. the output amplifer has a low impedance output and is designed to drive up to 200pf capacitive loads directly. capacitive loads exceeding 200pf should be decoupled with an external resistor of at least 100. shdn (pin 8): shutdown pin. when pulled to within 0.5v of gnd (pin 5), will place the lt1999 into low power shutdown. if the pin is left foating, an internal 2a pull- up current source will place the lt1999 into the active (amplifying) state.
LT1999-10/lt1999-20/ lt1999-50 13 1999fb shdn v + v + d1 v + v+ v+ v(g +in ) v(g ?in ) 2k r +in r ?in 300 c f 4pf 0.8k r +s 0.8k r ?s 160k 160k 1999 bd 2a out ref +in ?in gnd + ? + ? g in r g a o 2k 2k 4.5k 2k 8 7 2 1 3 4 6 5 b lock diagra m figure 1. simplified block diagram tes t c ircui t 5v 5v 1999 f02 0.1f v out v in(diff) + ? v cm v ref v shdn + ? + ? + ? lt1999 4k 0.8k 160k 160k 2a 0.8k 4k shdn v + v + v + + ? + ? 8 1 2 3 4 7 6 5 r g 0.1f v + v + figure 2. test circuit
LT1999-10/lt1999-20/ lt1999-50 14 1999fb the lt1999 current sense amplifer provides accurate bidirectional monitoring of current through a user-selected sense resistor. the voltage generated by the current fowing in the sense resistor is amplifed by a fxed gain of 10v/v, 20v/v or 50v/v (LT1999-10, lt1999-20, or lt1999-50 respectively) and is level shifted to the out pin. the volt- age difference and polarity of the out pin with respect to ref (pin 6) indicates magnitude and direction of the current in the sense resistor. t heor y of o pera tion refer to the block diagram (figure 1). case 1: v + < v cm < 80v for input common mode voltages exceeding the power supply, one can assume d1 of figure 1 is completely off. the sensed voltage (v sense ) is applied across pin 2 (+in) and pin 3 (Cin) to matched resistors r + in and r C in (nomi- nally 4k each). the opposite ends of r + in and r C in are forced to equal potentials by transconductor g in , which convert the differentially sensed voltage into a sensed current. the sensed current in r + in and r C in is combined, level-shifted, and converted back into a voltage by trans- resistance amplifer a o and resistor r g . amplifer a o pro- vides high open loop gain to accurately convert the sensed current back into a voltage and to drive external loads. the theoretical output voltage is determined by the sensed voltage (v sense ), and the ratio of two on-chip resistors: v out ? v ref = v sense ? r g r in where r in = r + in + r ? in 2 nominally 4k for the LT1999-10, r g is nominally 40k. for the lt1999-20, r g is nominally 80k, and for the lt1999-50, r g is nomi- nally 200k. a pplica t ions i n f or m a t ion the voltage difference between the out pin and the ref pin represent both polarity and magnitude of the sensed voltage. the noninverting input of amplifer a o is biased by a resistive 160k to 160k divider tied between v + and gnd to set the default ref pin bias to mid-supply. case 2: C5v < v cm < v + for common mode inputs which transition or are set below the supply voltage, diode d1 will turn on and will provide a source of current through r +s and r C s to bias the inputs of transconductance amplifer g in at least 2.25v above gnd. the transition is smooth and continuous; there are negligible changes to either gain or amplifer voltage off - set. the only difference in amplifer operation is the bias currents provided by d1 through r +s and r C s are steered through the input pins, otherwise amplifer operation is identical. the inputs to transconductance amplifer g in are still forced to equal potentials forcing any differential volt - ages appearing at the +in and Cin pins into a differential current. this differential current is combined, level-shifted, and converted back into a voltage by trans-resistance amplifer a o and resistor r g . resistors r +s and r C s are trimmed to match r + in and r C in respectively, to prevent common mode to differential conversion from occurring (to the extent of the matched trim) when the input com- mon mode transitions below v + . as described in case 1, the output is determined by the sense voltage and the ratio of two on-chip resistors: v out ? v ref = v sense ? r g r in where r in = r + in + r ? in 2
LT1999-10/lt1999-20/ lt1999-50 15 1999fb a pplica t ions i n f or m a t ion input common mode range the lt1999 was optimized for high common mode re - jection. its input stage is balanced and fully differential, designed to amplify differential signals and reject common mode signals. there is negligible crossover distortion due to sense voltage reversals. the amplifer is most linear in the zero-sense region. with the v + supply confgured within the specifed and tested range (4.5v < v + < 5.5v), the lt1999s common mode range extends from C5v to 80v. pushing +in and Cin beyond the limits specifed in the absolute maximum table can turn on the voltage clamps designed to protect the +in and Cin pins during esd events. it is possible to operate the lt1999 on power supplies as low as 4v (although it is not tested or specifed below 4.5v). operating the lt1999 on supplies below 4v will produce erratic behavior. when operating the lt1999 with supplies as low as 4v, the common mode range for inputs which extend below gnd is reduced. refer to the block diagram (figure 1). for inputs driven below v + , diode d1 conducts. for proper operation, the input to the transconductor v(g + in ) must be biased at approximately 2.25v above the gnd pin. v(g + in ) sits on the centertap of a voltage divider comprised of r + s and r + in v(g C in ) likewise sits in the middle of the voltage divider comprised of r C s , and r C in ). the voltage on v(g + in ) input is given by the following equation: v(g + in ) = v + in ? r + s r + s + r + in + v + ? v d1 ( ) ? r + in r + s + r + in setting v(g + in ) = 2.25v, the ratio (r + in /r + s ) to 5, and v d1 equal to 0.8v (cold temperatures), a plot of the lower input common mode range plotted against supply is shown in figure 3. output common mode range the lt1999s output common mode level is set by the voltage on the ref pin. the ref pin sits in the middle of a 160k to 160k voltage divider connected between v + and gnd which sets the default open circuit potential of the ref pin to mid-supply. it can be overdriven by an external voltage source capable of driving 80k tied to a mid-supply potential. see the electrical characteristics table for the ref pins specifed input voltage range. differential sampling of the out pin with respect the ref pin provides the best noise immunity. measurements of the output voltage made differentially with respect to the ref pin will provide the highest power supply and com - mon mode rejection. otherwise, power supply or gnd pin disturbances are divided by the ref pins voltage divider and appear directly at the noninverting input of the trans- resistance amplifer a o and are not rejected. if not driven by a low impedance (<100), the ref pin should be fltered with at least 1nf of capacitance to a low impedance, low noise ground plane. this external capacitance will also provide a charge reservoir during high frequency sampling of the ref pin by adc inputs attached to this pin. figure 3. lower input common mode vs supply voltage supply voltage (v) 4 v cm(lower limit) (v) ?2.0 ?2.5 ?3.0 ?4.0 ?5.0 ?3.5 ?4.5 ?5.5 ?6.0 4.75 4.25 5.25 1999 f03 5.5 4.5 5 below ground input common mode range limited by v + supply voltage below ground input common mode range limited by esd clamps typical esd clamp voltage
LT1999-10/lt1999-20/ lt1999-50 16 1999fb a pplica t ions i n f or m a t ion shutdown capability if shdn (pin 8) is driven to within 0.5v of gnd, the lt1999 is placed into a low power shutdown state in which the part will draw about 3a from the v + supply. the input pins (+in and Cin) will draw approximately 1na if biased within the range of 0v to 80v (with no differential voltage applied). if the input pins are pulled below the gnd pin, each input appears as a diode tied to gnd in series with approximately 4k of resistance. the ref pin appears as approximately 0.4m tied to a mid-supply potential. the output appears as reverse biased diodes tied between the output to either v + or gnd pins. emi filtering and layout practices an internal 1st order differential lowpass noise/emi sup- pression flter with a C3db bandwidth of 10mhz (approxi- mately 5 the lt1999s C3db bandwidth) is included to help improve the lt1999s emi susceptibility and to assist with the rejection of high frequency signals beyond the bandwidth of the lt1999 that may introduce errors. the pole is set by the following equation: f flt = 1/(?(r + in + r C in )?c f ) 10mhz both the resistors and capacitors have a 15% variation so the pole can vary by approximately 30% over manu - facturing process and temperature variations. the layout for lowest emi/noise susceptibility is achieved by keeping short direct connections and minimizing loop areas (see figure 4). if the user-supplied sense resistor cannot be placed in close proximity to the lt1999, the surface area of the loop comprising connections of +in to r sense and back to Cin should be minimized. this requires routing pcb traces connecting +in to r sense and Cin to r sense adjacent with one another with minimal separation. the metal traces connecting +in to the sense resistor and Cin to the sense resistor should match and use the same trace width. bypassing the v + pin to the gnd pin with a 0.1f capacitor with short wiring connection is recommended. figure 4. recommended layout supply bypass capacitor * keep loop area comprising r sense , +in and ?in pins as small as possible. ** ref bypass tied to a low noise, low impedance signal ground plane. ? optional 10pf capacitor to prevent dv/dt edges on input coupling to floating shdn pin. ** * from dc source to load r sense differential analog out ? 1999 f03 1 2 3 4 8 7 6 5 shdn out ref gnd v + +in ?in v +
LT1999-10/lt1999-20/ lt1999-50 17 1999fb a pplica t ions i n f or m a t ion the ref pin should be either driven by a low source im - pedance (<100) or should be bypassed with at least 1nf to a low impedance, low noise, signal ground plane (see figure 4). larger bypass capacitors on both v + pins, and the ref pin, will extend enhanced ac cmrr, and psrr performance to lower frequencies. bypassing the ref pin to a quiet ground plane flters the v + pin or gnd pin noise that is sensed by the ref pin voltage divider and applied to the noninverting input of output amplifer a o . any com- mon i?r drops generated by pulsating ground currents in common with the ref pin flter capacitor can compromise the fltering performance and should be avoided. if the shdn pin is not driven and is left foating, routing a pcb trace connecting pins 1 and 8 under the part will act as a shield, and will help limit edge coupling from the inputs (pins 2 and 3) to the shdn pin. periodic pulses on the inputs with fast edges may glitch the high impedance shdn pin, periodically putting the part into low power shutdown. additional precaution against this may be taken by adding an optional small (~10pf) capacitor may be tied between v + (pin 1) and pin 8. finally, when connecting the lt1999 inputs to the sense resistor, it is important to use good kelvin sensing practices (sensing the resistor in a way that excludes pcb trace i?r voltage drops). for sense resistors less than 1, one might consider using a 4-wire sense resistor to sense the resistive element accurately. selection of the current sense resistor the external sense resistor selection presents a delicate trade-off between power dissipation in the resistor and current measurement accuracy. in high current applications, the user may want to mini- mize the power dissipated in the sense resistor. the sense resistor current will create heat and voltage loss, degrading effciency. as a result, the sense resistor should be as small as possible while still providing adequate dynamic range required by the measurement. the dynamic range is the ratio between the maximum accurately produced signal generated by the voltage across the sense resistor, and the minimum accurately reproduced signal. the minimum accurately reproduced signal is primarily dictated by the voltage offset of the lt1999. the maximum accurately reproduced signal is dictated by the output swing of the lt1999. thus the dynamic range for the lt1999 can be thought of the maximum sense voltage divided by the input referred voltage offset or: dynamic range = ? v out(max) gain s v osi the above equation tells us that the dynamic range is inversely proportional to the gain of the lt1999. thus, if accuracy is of greater importance than effciency or power loss, the LT1999-10 used with the highest valued sense resistor possible is recommended. if effciency, heat generated, and power loss in the resistive shunt is the primary concern, the lt1999-50 and the lowest value sense resistor possible is recommended. the lt1999-20 is available for applications somewhere in between these two extremes.
LT1999-10/lt1999-20/ lt1999-50 18 1999fb a pplica t ions i n f or m a t ion v out v ref v shdn lt1999 4k 0.8k 160k 160k 2a 0.8k 4k shdn v + v + v + + ? + ? 8 1 2 3 4 7 6 5 r g v + v + v s 5v 1999 f05 0.1f 0.1f fuse steering diode load i load r sense offon 5v v out v +in v ?in v ref v shdn figure 5. using the lt1999 to monitor a fuse fuse monitor the inputs can be overdriven without fear of damaging the lt1999. this makes the lt1999 ideal for monitoring fuses if either +in or Cin are shorted to ground while the other is at the full common mode supply voltage (see figure 5). if the fuse in figure 5 opens with the +in tied to the positive supply, the load will pull Cin to gnd. the output will be forced to the positive v + supply rail. if it is desired that the output be near ground if the fuse opens, it is a simple matter of swapping the inputs. precautions should be followed: first, when the inputs are stressed differentially due to the fuse blowing open, a large voltage drop will be placed across the +in to Cin pins, dissipating power in the precision on-chip input resistors. precaution should be taken to prevent junction temperatures from exceeding the absolute maximum ratings (see note 3 in the electrical characteristics section). secondly, if the load is inductive, and the fuse blows open without a clamp diode, energy stored in the inductive load will be dissipated in the lt1999, which could cause damage. a simple steering diode as shown in figure 5 will prevent this from happen - ing, and will protect the lt1999 from damage. finally, the user should be aware that in fuse monitoring applications with the sense voltage (v sense = v + in C v C in ) being driven in excess of C25v, the output of the lt1999 will undergo phase reversal (see figure 6). figure 6. a plot of the lt1999s output voltage vs v sense (v sense = v +in C v C in ). in applications where the sense voltage is driven in excess of C25v, the output of the lt1999 will undergo phase reversal v sense (v) ?60 v out (1v/div) ?30?45 ?15 30 1999 f06 60 15 45 0 v out phase reversal for v sense < ?25v v ref = 2.5v
LT1999-10/lt1999-20/ lt1999-50 19 1999fb typical a pplica t ions solenoid current monitor the solenoid of figure 7 consists of a coil of wire in an iron case with permeable plunger that acts as a movable element. when the mosfet turns on, the diode is reversed biased off, and current fows through r sense to actuate the solenoid. if the mosfet is turned off, the current in the mosfet is interrupted, but the energy stored in the solenoid causes the diode to turn on and current to freewheel in the loop consisting of the diode, r sense and the solenoid. figure 7 shows the lt1999 monitoring currents in a ground referenced solenoid used when the coil is hard tied to the case, and is tied to ground. figure 8 shows a supply referenced solenoid whose coil is insulated from the case. the lt1999 will interface equally well to either of these two confgurations. bidirectional pwm motor monitor pulse width modulation is commonly used to effciently vary the average voltage applied across a dc motor. the h-bridge topology of figure 9 allows full 4-quadrant control: clockwise control, counter-clockwise control, clockwise regeneration, and counter-clockwise regeneration. the lt1999 in conjunction with a non-inductive current shunt is used to monitor currents in the rotor. the lt1999 can be used to detect stuck rotors, provide detection of over - current conditions in general, or provide current mode feedback control. figure 10 shows a plot of the output voltage of the lt1999. figure 7. solenoid current monitor for ground tied solenoid. the common mode inputs to the lt1999 switch between v s and one diode drop below ground lt1999 4k 0.8k 160k 160k 2a 0.8k 4k shdn v + v + v + + ? + ? 8 1 2 3 4 7 6 5 r g v + v + time (50ms/div) v out (0.5v/div) v +in (10v/div) 5v v s 5v 1999 f07a 1999 f07b 0.1f 0.1f solenoid r sense v +in v shdn v out v ref v ?in on off v out v +in solenoid plunger pulls in solenoid releases 2.5v
LT1999-10/lt1999-20/ lt1999-50 20 1999fb figure 8. solenoid current monitor for non-grounded solenoids. this circuit performs the same function as figure 7 except one end of the solenoid is tied to v s . the common mode voltage of inputs of the lt1999 switch between ground and one diode drop above v s typical a pplica t ions lt1999 4k 0.8k 160k 160k 2a 0.8k 4k shdn v + + ? + ? 8 2 3 7 6 5 r g v + v + 5v v s 5v 1999 f08a 1 4 0.1f 2.5v 0.1f solenoid r sense v out v ref v shdn on off v + v + v +in v ?in time (50ms/div) v out (0.5v/div) v +in (10v/div) v out v +in solenoid plunger pulls in solenoid releases 1999 f08b
LT1999-10/lt1999-20/ lt1999-50 21 1999fb typical a pplica t ions figure 9. armature current monitor for dc motor applications figure 10. lt1999 output waveforms for the circuit of figure 9 1999 f09 v bridge v +in v ?in r sense 0.025 10f pwm input direction brake input 24v 5v 5v gnd 5v pwm in outa outb c4 1000f 24v motor h-bridge lt1999-20 4k 0.8k 160k 160k 2a 0.8k 4k shdn + ? + ? 80k v + v + v + v + 0.1f 0.1f 8 7 6 v shdn v out v ref 2 3 1 4 v + 5 time (20s/div) v out (2v/div) v +in (20v/div) 1999 f10 v out v +in 2.5v
LT1999-10/lt1999-20/ lt1999-50 22 1999fb p ackage descrip t ion s8 package 8-lead plastic small outline (narrow .150 inch) (reference ltc dwg # 05-08-1610) please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. .016 ? .050 (0.406 ? 1.270) .010 ? .020 (0.254 ? 0.508) 45 0? 8 typ .008 ? .010 (0.203 ? 0.254) so8 0303 .053 ? .069 (1.346 ? 1.752) .014 ? .019 (0.355 ? 0.483) typ .004 ? .010 (0.101 ? 0.254) .050 (1.270) bsc 1 2 3 4 .150 ? .157 (3.810 ? 3.988) note 3 8 7 6 5 .189 ? .197 (4.801 ? 5.004) note 3 .228 ? .244 (5.791 ? 6.197) .245 min .160 .005 recommended solder pad layout .045 .005 .050 bsc .030 .005 typ inches (millimeters) note: 1. dimensions in 2. drawing not to scale 3. these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .006" (0.15mm) ms8 package 8-lead plastic msop (reference ltc dwg # 05-08-1660 rev f) msop (ms8) 0307 rev f 0.53 0.152 (.021 .006) seating plane note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.18 (.007) 0.254 (.010) 1.10 (.043) max 0.22 ? 0.38 (.009 ? .015) typ 0.1016 0.0508 (.004 .002) 0.86 (.034) ref 0.65 (.0256) bsc 0 ? 6 typ detail ?a? detail ?a? gauge plane 1 2 3 4 4.90 0.152 (.193 .006) 8 7 6 5 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) 0.52 (.0205) ref 5.23 (.206) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.42 0.038 (.0165 .0015) typ 0.65 (.0256) bsc
LT1999-10/lt1999-20/ lt1999-50 23 1999fb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 5/11 revised +in and Cin pin descriptions in pin functions section 12 b 3/12 revised voltage output swing low specification (v out ) under a loaded condition of 1k? to mid-supply. updated figure 4 to multicolor. 4, 6 16
LT1999-10/lt1999-20/ lt1999-50 24 1999fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax : (408) 434-0507 l www.linear.com ? linear technology corporation 2010 lt 0312 rev b ? printed in usa typical a pplica t ion part number description comments lt1787/ lt1787hv precision, bidirectional high side current sense amplifier 2.7v to 60v operation, 75v offset, 60a current draw lt6100 gain-selectable high side current sense amplifier 4.1v to 48v operation, pin-selectable gain: 10v/v, 12.5v/v, 20v/v, 25v/v, 40v/v, 50v/v ltc6101/ ltc6101hv high voltage high side current sense amplifier 4v to 60v/5v to 100v operation, external resistor set gain, sot23 ltc6102/ ltc6102hv zero drift high side current sense amplifier 4v to 60v/5v to 100v operation, 10v offset, 1s step response, msop8/dfn packages ltc6103 dual high side precision current sense amplifier 4v to 60v, gain configurable, 8-pin msop package ltc6104 bidirectional, high side current sense 4v to 60v, gain configurable, 8-pin msop package lt6106 low cost, high side precision current sense amplifier 2.7v to 36v, gain configurable, sot23 package lt6105 precision, extended input range current sense amplifier C0.3 to 44v, gain configurable, 8-pin msop package ltc4150 coulomb counter/battery gas gauge indicates charge quantity and polarity lt1990 precision, 100a gain selectable amplifier 2.7v to 36v operation, cmrr > 70db, input voltage = 250v lt1991 250v input range difference amplifier 2.7v to 36v operation, 50v offset, cmrr > 75b, input voltage = 60v lt1637/lt1638 1.1/1.2mhz, 0.4v/s over-the-top, rail-to-rail input and output amplifier 0.4v/s slew rate, 230a per amplifier r ela t e d p ar t s 1999 ta02 5v 0.1f LT1999-10 4k 0.8k 160k 160k 2a 0.8k 4k v + + ? shdn + ? v out 40k v ref v shdn v + v + v + v + 4 0.1f 5v charger load 0.025 bat 42v v cc v ref 0.1f +in 10f cs sck sdo ltc2433-1 v out + ? 5v ?in 0.1f 2 3 1 5 7 6 8 v +in v ?in battery charge current and load current monitor v out = 0.25v/a, maximum measured current 9.5a

▲Up To Search▲

Price & Availability of LT1999-10

	To Download LT1999-10 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .